The present invention relates to a semiconductor memory device, and more particularly to an address input path selection circuit which determines which one of a number of banks an address will be input to in the semiconductor memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes an address buffer 101, a Y-address controller 102, banks (0˜3) 103, a command decoder 104, a read/write signal generator 105, address input path selection circuits 106, and a Yi signal generator 107.
The address buffer 101 receives and buffers bank addresses BAN<0:1> and addresses AN<0:11> to output buffered addresses EAT_AX<0:11>. Furthermore, the address buffer 101 decodes the bank addresses BAN<0:1> to output bank information BANK<0:3>. The Y-address controller 102 outputs a Y-address signal Y-ADDRESS, which is input to the banks 103 to control the timing of addressing, in response to the buffered addresses EAT_AX<0:11>, an internal write signal CASP6WT and an internal read signal CASP6RD.
The command decoder 104 receives and decodes external command signals, for example, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, thereby outputting the internal write signal CASP6WT and the internal read signal CASP6RD. The read/write signal generator 105 receives the internal read signal CASP6RD, the internal write signal CASP6WT and the bank information BANK<0:3>, and generates bank-specific read/write signals CASP8X<0:3>, which are respectively activated in the read or write operations of the corresponding bank.
For example, the bank-specific read/write signal CASP8X<0> for the bank 0 is activated when the internal read signal CASP6RD or the internal write signal CASP6WT is activated in a state where the bank 0 is selected, i.e., the BANK<0> is activated.
The Yi signal generator 107 generates signals YAE<0:3> which are the source signal of a Yi signal for turning on/off a Yi transistor of a semiconductor memory device. That is, the signals YAE<0:3> are a pulse signal for controlling the Yi transistor.
As many address input path selection circuits 106 as the banks 103 are provided to output Y-address input enable signals CAST10<0:3> of the respective banks. When the Y-address input enable signals CAST10<0:3> are activated, the Y-address signal Y-ADDRESS and the signals YAE<0:3> are input to the corresponding banks.
For example, when the Y-address input enable signal CAST10<0> for the bank 0 is activated, the Y-address signal Y-ADDRESS and the signal YAE<0> are input to the bank 0.
Meanwhile, the banks 103 are illustrated as a single configuration block in FIG. 1, but the banks 103 indicate four banks, i.e., the banks 0, 1, 2 and 3.
FIG. 2 is a circuit diagram illustrating one of the address input path selection circuits 106 of FIG. 1.
Specifically, FIG. 2 illustrates the address input path selection circuit configured to output the Y-address input enable signal CAST10<0> for the bank 0.
Upon operation of the address input path selection circuit, when the internal read signal CASP6RD is activated by the combination of commands input to the command decoder 104, the bank-specific read/write signal CASP8X<0> for the bank 0 is activated. Then, the Y-address input enable signal CAST10<0> is activated so that the Y-address signal Y-ADDRESS and the signal YAE<0> are input to the bank 0.
Furthermore, when the bank-specific read/write signal CASP8X<0> for the bank 0 is activated continuously, the Y-address input enable signal CAST10<0> is kept at a high level. However, when the internal read signal CASP6RD or the internal write signal CASP6WT is activated in a state where the bank-specific read/write signal CASP8X<0> for the bank 0 is deactivated (that is, during the read or write operations of other banks), the Y-address input enable signal CAST10<0> is deactivated to a low level. At this point, one of the Y-address input enable signals CAST10<1:3> for other banks is activated.
FIG. 3 is a timing diagram illustrating the operation of the address input path selection circuit of FIG. 2. It can be seen from FIG. 3 that the Y-address input enable signal CAST10<0> is activated or deactivated in an above-described manner.
The conventional address input path selection circuits 106 generate the Y-address input enable signals CAST10<0:3> by combining the bank-specific read/write signals CASP8X<0:3>, the internal read signal CASP6RD and the internal write signal CASP6WT. However, since the bank-specific read/write signals CASP8X<0:3>, the internal read signal CASP6RD, and the internal write signal CASP6WT have passed a different number of gates, the conventional address input path selection circuits 106 require a lot of delay elements 201, 202 and 203 for adjusting the timing of these signals. Since as many address input path selection circuits 106 as the banks 103 are needed, the address input path selection circuits 106 will occupy a large area in the semiconductor memory device.
Since the Y-address input enable signals CAST10<0:3> which allow the Y-address signal Y-ADDRESS to be input to a selected bank are signals associated with a column operation, they are needed only in the bank active state. However, in a case where the Y-address input enable signals CAST10<0:3> are generated by the circuit shown in FIG. 2, at least one of the Y-address input enable signals CAST10<0:3> is necessarily activated when the semiconductor memory device operates. Accordingly, malfunction may occur when the read/write operating command is input irrespective of the column operation.